11/29/03 - Decicon announces High-Speed Logic and Interface building blocks for TSMC 0.18µm CMOS process
Decicon announces the availability of silicon proven High-Speed Logic and Interface building blocks for TSMC 0.18µm CMOS process. The building blocks include "IF02 - LVDS Transmitter", "IF03 - LVDS Receiver" and "LI01 - CML Core Library". The building blocks are designed for the logic version of TSMC 0.18µm process and are compatible with all versions of 0.18µm process from TSMC.
IF02 is a differential line driver that complies with ANSI TIA/EIA-644A standard and is guaranteed to transmit data at speeds up to 622Mb/s. The patent pending architecture of IF02 allows fast and glitch-free mode transitions between tri-state and normal operating modes. IF02 is compatible with multi-drop applications. Companion receiver is IF03.
IF03 is a differential line receiver that complies with ANSI TIA/EIA-644A standard and is guaranteed to receive data at speeds up to 622Mb/s. Companion transmitter is IF02.
LI01 is a complete CML core library designed for applications requiring very high-speed logic. The maximum operating speed can be lowered if lower power consumption is desired. More than 30 cells are available in the library. A custom bias generator is also included for optimum swing matching and chip level tracking.
Contact Decicon at email@example.com or call (408) 261-1442 Ext. 1# for more information.